Join a diverse team of silicon engineers to design and develop next-gen SoCs, pushing the boundaries of technology.
Your Role:
Key responsibilities as follows:
- Develop test plans and verification infrastructure for RTL design blocks.
- Build verification testbench environments using SV/UVM, C, Python, and YAML.
- Create reusable models, monitors, checkers, and scoreboards.
- Drive coverage-driven verification closure and verify protocol functionalities.
- Perform regression triage and collaborate with architects, designers, and post-silicon teams.
- Work with cross-functional teams to identify coverage scope.
- Utilize System Verilog/Verilog RTL coding and build simulation workflows.
- Develop physical design implementations for low power designs.
- Resolve power issues and perform comprehensive power analysis.
About You:
The ideal candidate will have:
- A Bachelor’s or Master’s Degree in Electrical Engineering or related field.
- Anticipated graduation date between December 2025 and August 2026.
- Experience in VLSI, hardware design languages, analog and digital circuits, DSP systems, and quantum mechanics for engineers.
Compensation & Benefits:
Compensation varies by location, with hourly salary ranges from $20.34 to $66.63. Benefits include healthcare and other perks.
Training & Development:
Opportunities for professional growth through development programs and mentorships.
Career Progression:
Potential for career advancement in the semiconductor industry, with growth expected over the next few years.
How to Apply:
Applications are accepted on an ongoing basis. Submit your application with the required details and qualifications.
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